Semiconductor memory devices are comprised of an array of memory cells. Each memory cell comprises a capacitor, on which the charge stored represents the logical state of the memory cell. A charged capacitor corresponds to a logical state of "1" and an uncharged capacitor corresponds to a logical state of "0." Word lines activate access transistors, so that the logical state of a memory cell can be read. Gates of multiple transistors are formed as one word line.
An example of a word line's application is in a dynamic random access memory (DRAM). In a DRAM, a common word line, used to access memory cells, is fabricated on a p-type silicon substrate coated with a thin film of silicon dioxide (SiO.sub.2), known as gate oxide. Then, a word line is formed on the gate oxide later as a two-layer stack, comprising silicon (or polysilicon), coated with a conductor material. The most common two-layer stack used in the industry is a layer of polysilicon, coated with a tungsten silicide layer. Tungsten silicide is used because of its good integration properties, such as providing good thermal stability, stability during source/drain oxidation, and stability during dry etching, as well as having; a low resistivity. Although titanium silicide is approximately 75% less resisitive than tungsten silicide, it has not been used extensively in two-layer stacks because it is not as thermally stable. Titanium silicide tends to agglomerate during subsequent high temperature processing steps. Alternatively, a metal is used instead of a silicide for the conductor layer.
Of primary concern is minimizing resistivity throughout the word line, due to the need to reduce RC time constants and access multiple memory cells in as short a period of time as possible. The problem is especially critical due to the extended length of word lines. Diffusion of silicon from the bottom polysilicon layer to the top conductor layer increases the resistivity of the two-layer stack When silicon diffuses through the stack, it reacts with the conductor layer elements, increasing the resistivity of the conductor layer. When the conductor layer is formed of a metal, silicides are formed, which have a higher resistivity than pure metal.
One previous unsuccessful attempt to solve this diffusion problem introduces a third layer, which acts as a diffusion barrier, between the silicon and conductor layers. For example, a silicon nitride layer is used as the third layer in a two-layer stack. However, the silicon nitride diffusion barrier layer of Ito et al. (IEEE Transactions on Electron Devices, ED-33 (1986), 464 and U.S. Pat. No. 4,935,804) is difficult to employ because it must be ultrathin (less than 3 nanometers thick) to allow tunneling of charges through the layer, yet thick enough to act as a reaction barrier between the polysilicon and conductor layer elements.
Another diffusion barrier used in the past comprises a titanium nitride layer interposed between a two-layer stack. The conductive titanium nitride barrier layer of Pan et al. (IBM General Technology Division, "Highly Conductive Electrodes for CMOS") attempts to solve the problems of Ito et al., but it requires a special source/drain (S/D) oxidation process when forming oxide spacers to maintain gate oxide layer integrity. A special process is required due to the tendency for tungsten and titanium nitride to oxidize, resulting in degradation of these layers. This adds time and cost to the fabrication process.
In ultra large scale integrated (ULSI) circuits, a highly conductive word line is necessary to improve circuit density and performance. In order to maintain a highly conductive word line, it is necessary to provide an effective method for decreasing diffusion within the two-layer stack. As devices are scaled down in size, word line widths are also decreased. While smaller line widths result in a decreased amount of resistance, this decrease is more than offset by an increase resistance due to the longer length of word lines. To date, word line resistance is one of the primary limitations of achieving faster ULSI circuits. A method for decreasing the resistivity of word lines is needed for use in ULSI applications.
In addition to creating a diffusion barrier layer in a two-layer word line stack, another way of decreasing resistance in a word line is by forming a high conductivity film on the word line. Such films are commonly formed of a refractory metal silicide, such as titanium silicide (TiSi.sub.2). Titanium is preferably used as the refractory metal component because it has the ability to reduce oxygen, which remains on surfaces in the form of native oxides. Native oxides are reduced to titanium oxide by titanium. Native oxides degrade interface stability, and often cause device failure if not removed.
However, several problems occur with the use of TiSi.sub.2 in ULSI applications. At higher temperatures subsequent processing temperatures, TiSi.sub.2 has a tendency to agglomerate into two different phases, C54 and C49, which have different lattice structures. The C54 phase agglomerates at the interfaces between C49-TiSi.sub.2 and silicon (or polysilicon). While this is undesirable due to the increased resistance associated with agglomeration, the TiSi.sub.2 phase formed at higher temperatures, C54, is more stable and has a much lower resistivity than the C49 metastable phase formed at lower temperatures.
Another problem with using TiSi.sub.2 at higher temperatures is that the high-temperature phase, C54, has a grain size typically ranging from 0.3 to over 1.0 microns, which prohibits it from being used in sub-0.25 micron word line applications. However, it is always desirable to form a phase having the lowest free energy at a particular grain size, so that it is the most stable. FIG. 1 illustrates how free energy, .DELTA.G.sub.f (.gamma.), is a function of grain size, r. Free energy, .DELTA.G.sub.f (.gamma.), as a function of grain size, r, is divided into three regions: A, B, and C. The most stable phase at a given grain size is that which has the lowest free energy. Both regions A and B are in the sub-micron range. In the sub-micron range, the free energy of C54 is greater than that of C49, due to the larger surface energy of C54.
In order to use the C54 phase in ULSI circuits, particularly in 256 Megabit DRAMs and other devices requiring sub-0.25 micron line widths, it is necessary that the grain size be reduced, so that it will be more stable. Due to the increased sensitivity of ULSI circuits, it is important to maintain low resistivity in ULSI devices. There is a need for a stable, low resistivity TiSi.sub.2 phase which can be used in sub-0.25 micron word line applications.